The invention relates to a method for the galvanic manufacture of metallic, bump-like lead contacts of semiconductor components wherein the lead contacts are formed of etchable metals having a surface coating of gold.
In the modern semiconductor industry, specifically in the fabrication of integrated semiconductor components, automatic tape assembly ("Tape Automatic Bonding", TAB) is being employed to an increasing degree. One of the basic prerequisites in semiconductor manufacture according to this TAB technology is that the semiconductor component (chip) does not, as was hitherto usual, have metallized contact surfaces at the locations (pads) provided for contacting which, for example, consist of aluminum. Rather, the chip has bump-like, metallic lead contacts (consisting, for example, of copper) which project above the chip surface.
As known, cuprous lead contacts oxidize at the surface given long storage, this reducing the solderability which is normally good for copper. In order to prevent this, such lead contacts are generally coated with a sufficiently thick gold layer. Even at room temperature, however, this gold layer diffuses into the surface of the lead contact to a certain degree, and this has to be taken into consideration in the identification of the required thickness of the gold coating.
A thin, metallic layer sequence which acts as an adhesion layer and diffusion barrier is situated between the lead contacts and the corresponding chip-internal interconnects. This, for example, consists of titanium and copper or of titanium-tungsten and copper. Known manufacturing methods for the thin, metallic layer sequence and for the lead contacts consist of vapor-depositing or sputtering the individual materials employed onto the semiconductor element in surface-wide fashion and masking by standard photolithographic methods, such as with photoresist at those locations at which the lead contacts are to be produced. The previously vapor-deposited materials are in turn etched off by means of a wet-chemical method in the remaining, unmasked regions of the chip. Given a surface-wide sputtering of the semiconductor circuit with the material for creating the lead contacts, for example copper to a thickness of 20 .mu.m, too high a sputtering heat and different coefficients of thermal expansion of the basic semiconductor material (generally silicon) and of the lead contact material (copper) also are present. All of this leads to a risk that considerable sags of the semiconductor wafers to be processed, stresses, crystal fractures, and cracks will arise within the semiconductor component, and that damage (cracks) in the so-called final passivation layer applied to the surface of the semiconductor in order to protect against the mechanical damage will occur. For example, the following sags in approximately 400 .mu.m thick silicon wafers given a copper application of respectively 20 .mu.m have been measured:
in 3-inch wafers--180 .mu.m.+-.20 .mu.m, PA0 in 4-inch wafers--300 .mu.m.+-.40 .mu.m.
In addition to the mechanical damage described above, mis-adjustments in the following phototechnique masking also occur due to the sagging.
When, instead of executing the steps of surface-wide sputtering, phototechnique steps, and etching of excess copper material, lead contacts of copper are electro-deposited, then the damage described above does not occur. A new problem, however, arises as described hereafter.
After the electro-deposition of the lead contacts, the thin, metallic layer sequence that has at first been applied surface-wide must again be etched off in the regions outside of the lead contacts. In this etching process, however, the lead contacts are also attacked, whereby considerable causticization appears at the contacts, this leading to considerable failures in a solder bonding executed later as a consequence of the differing etching erosion.